/*
Copyright (C) 2018-2019 de4dot@gmail.com

Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:

The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/

use core::fmt;

// GENERATOR-BEGIN: CodeSize
// ⚠️This was generated by GENERATOR!🦹‍♂️
/// The code size (16/32/64) that was used when an instruction was decoded
#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Hash)]
pub enum CodeSize {
	/// Unknown size
	Unknown = 0,
	/// 16-bit code
	Code16 = 1,
	/// 32-bit code
	Code32 = 2,
	/// 64-bit code
	Code64 = 3,
}
#[cfg_attr(feature = "cargo-fmt", rustfmt::skip)]
static GEN_DEBUG_CODE_SIZE: [&str; 4] = [
	"Unknown",
	"Code16",
	"Code32",
	"Code64",
];
impl fmt::Debug for CodeSize {
	#[inline]
	fn fmt<'a>(&self, f: &mut fmt::Formatter<'a>) -> fmt::Result {
		write!(f, "{}", GEN_DEBUG_CODE_SIZE[*self as usize])?;
		Ok(())
	}
}
impl Default for CodeSize {
	#[cfg_attr(has_must_use, must_use)]
	#[inline]
	fn default() -> Self {
		CodeSize::Unknown
	}
}
// GENERATOR-END: CodeSize

// GENERATOR-BEGIN: RoundingControl
// ⚠️This was generated by GENERATOR!🦹‍♂️
/// Rounding control
#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Hash)]
pub enum RoundingControl {
	/// No rounding mode
	None = 0,
	/// Round to nearest (even)
	RoundToNearest = 1,
	/// Round down (toward -inf)
	RoundDown = 2,
	/// Round up (toward +inf)
	RoundUp = 3,
	/// Round toward zero (truncate)
	RoundTowardZero = 4,
}
#[cfg_attr(feature = "cargo-fmt", rustfmt::skip)]
static GEN_DEBUG_ROUNDING_CONTROL: [&str; 5] = [
	"None",
	"RoundToNearest",
	"RoundDown",
	"RoundUp",
	"RoundTowardZero",
];
impl fmt::Debug for RoundingControl {
	#[inline]
	fn fmt<'a>(&self, f: &mut fmt::Formatter<'a>) -> fmt::Result {
		write!(f, "{}", GEN_DEBUG_ROUNDING_CONTROL[*self as usize])?;
		Ok(())
	}
}
impl Default for RoundingControl {
	#[cfg_attr(has_must_use, must_use)]
	#[inline]
	fn default() -> Self {
		RoundingControl::None
	}
}
// GENERATOR-END: RoundingControl

// GENERATOR-BEGIN: OpKind
// ⚠️This was generated by GENERATOR!🦹‍♂️
/// Instruction operand kind
#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Hash)]
#[allow(non_camel_case_types)]
pub enum OpKind {
	/// A register ([`Register`]).
	///
	/// This operand kind uses [`Instruction::op0_register()`], [`Instruction::op1_register()`], [`Instruction::op2_register()`], [`Instruction::op3_register()`] or [`Instruction::op4_register()`] depending on operand number. See also [`Instruction::op_register()`].
	///
	/// [`Register`]: enum.Register.html
	/// [`Instruction::op0_register()`]: struct.Instruction.html#method.op0_register
	/// [`Instruction::op1_register()`]: struct.Instruction.html#method.op1_register
	/// [`Instruction::op2_register()`]: struct.Instruction.html#method.op2_register
	/// [`Instruction::op3_register()`]: struct.Instruction.html#method.op3_register
	/// [`Instruction::op4_register()`]: struct.Instruction.html#method.op4_register
	/// [`Instruction::op_register()`]: struct.Instruction.html#method.op_register
	Register = 0,
	/// Near 16-bit branch. This operand kind uses [`Instruction::near_branch16()`]
	///
	/// [`Instruction::near_branch16()`]: struct.Instruction.html#method.near_branch16
	NearBranch16 = 1,
	/// Near 32-bit branch. This operand kind uses [`Instruction::near_branch32()`]
	///
	/// [`Instruction::near_branch32()`]: struct.Instruction.html#method.near_branch32
	NearBranch32 = 2,
	/// Near 64-bit branch. This operand kind uses [`Instruction::near_branch64()`]
	///
	/// [`Instruction::near_branch64()`]: struct.Instruction.html#method.near_branch64
	NearBranch64 = 3,
	/// Far 16-bit branch. This operand kind uses [`Instruction::far_branch16()`] and [`Instruction::far_branch_selector()`]
	///
	/// [`Instruction::far_branch16()`]: struct.Instruction.html#method.far_branch16
	/// [`Instruction::far_branch_selector()`]: struct.Instruction.html#method.far_branch_selector
	FarBranch16 = 4,
	/// Far 32-bit branch. This operand kind uses [`Instruction::far_branch32()`] and [`Instruction::far_branch_selector()`]
	///
	/// [`Instruction::far_branch32()`]: struct.Instruction.html#method.far_branch32
	/// [`Instruction::far_branch_selector()`]: struct.Instruction.html#method.far_branch_selector
	FarBranch32 = 5,
	/// 8-bit constant. This operand kind uses [`Instruction::immediate8()`]
	///
	/// [`Instruction::immediate8()`]: struct.Instruction.html#method.immediate8
	Immediate8 = 6,
	/// 8-bit constant used by the `ENTER`, `EXTRQ`, `INSERTQ` instructions. This operand kind uses [`Instruction::immediate8_2nd()`]
	///
	/// [`Instruction::immediate8_2nd()`]: struct.Instruction.html#method.immediate8_2nd
	Immediate8_2nd = 7,
	/// 16-bit constant. This operand kind uses [`Instruction::immediate16()`]
	///
	/// [`Instruction::immediate16()`]: struct.Instruction.html#method.immediate16
	Immediate16 = 8,
	/// 32-bit constant. This operand kind uses [`Instruction::immediate32()`]
	///
	/// [`Instruction::immediate32()`]: struct.Instruction.html#method.immediate32
	Immediate32 = 9,
	/// 64-bit constant. This operand kind uses [`Instruction::immediate64()`]
	///
	/// [`Instruction::immediate64()`]: struct.Instruction.html#method.immediate64
	Immediate64 = 10,
	/// An 8-bit value sign extended to 16 bits. This operand kind uses [`Instruction::immediate8to16()`]
	///
	/// [`Instruction::immediate8to16()`]: struct.Instruction.html#method.immediate8to16
	Immediate8to16 = 11,
	/// An 8-bit value sign extended to 32 bits. This operand kind uses [`Instruction::immediate8to32()`]
	///
	/// [`Instruction::immediate8to32()`]: struct.Instruction.html#method.immediate8to32
	Immediate8to32 = 12,
	/// An 8-bit value sign extended to 64 bits. This operand kind uses [`Instruction::immediate8to64()`]
	///
	/// [`Instruction::immediate8to64()`]: struct.Instruction.html#method.immediate8to64
	Immediate8to64 = 13,
	/// A 32-bit value sign extended to 64 bits. This operand kind uses [`Instruction::immediate32to64()`]
	///
	/// [`Instruction::immediate32to64()`]: struct.Instruction.html#method.immediate32to64
	Immediate32to64 = 14,
	/// `seg:[SI]`. This operand kind uses [`Instruction::memory_size()`], [`Instruction::memory_segment()`], [`Instruction::segment_prefix()`]
	///
	/// [`Instruction::memory_size()`]: struct.Instruction.html#method.memory_size
	/// [`Instruction::memory_segment()`]: struct.Instruction.html#method.memory_segment
	/// [`Instruction::segment_prefix()`]: struct.Instruction.html#method.segment_prefix
	MemorySegSI = 15,
	/// `seg:[ESI]`. This operand kind uses [`Instruction::memory_size()`], [`Instruction::memory_segment()`], [`Instruction::segment_prefix()`]
	///
	/// [`Instruction::memory_size()`]: struct.Instruction.html#method.memory_size
	/// [`Instruction::memory_segment()`]: struct.Instruction.html#method.memory_segment
	/// [`Instruction::segment_prefix()`]: struct.Instruction.html#method.segment_prefix
	MemorySegESI = 16,
	/// `seg:[RSI]`. This operand kind uses [`Instruction::memory_size()`], [`Instruction::memory_segment()`], [`Instruction::segment_prefix()`]
	///
	/// [`Instruction::memory_size()`]: struct.Instruction.html#method.memory_size
	/// [`Instruction::memory_segment()`]: struct.Instruction.html#method.memory_segment
	/// [`Instruction::segment_prefix()`]: struct.Instruction.html#method.segment_prefix
	MemorySegRSI = 17,
	/// `seg:[DI]`. This operand kind uses [`Instruction::memory_size()`], [`Instruction::memory_segment()`], [`Instruction::segment_prefix()`]
	///
	/// [`Instruction::memory_size()`]: struct.Instruction.html#method.memory_size
	/// [`Instruction::memory_segment()`]: struct.Instruction.html#method.memory_segment
	/// [`Instruction::segment_prefix()`]: struct.Instruction.html#method.segment_prefix
	MemorySegDI = 18,
	/// `seg:[EDI]`. This operand kind uses [`Instruction::memory_size()`], [`Instruction::memory_segment()`], [`Instruction::segment_prefix()`]
	///
	/// [`Instruction::memory_size()`]: struct.Instruction.html#method.memory_size
	/// [`Instruction::memory_segment()`]: struct.Instruction.html#method.memory_segment
	/// [`Instruction::segment_prefix()`]: struct.Instruction.html#method.segment_prefix
	MemorySegEDI = 19,
	/// `seg:[RDI]`. This operand kind uses [`Instruction::memory_size()`], [`Instruction::memory_segment()`], [`Instruction::segment_prefix()`]
	///
	/// [`Instruction::memory_size()`]: struct.Instruction.html#method.memory_size
	/// [`Instruction::memory_segment()`]: struct.Instruction.html#method.memory_segment
	/// [`Instruction::segment_prefix()`]: struct.Instruction.html#method.segment_prefix
	MemorySegRDI = 20,
	/// `ES:[DI]`. This operand kind uses [`Instruction::memory_size()`]
	///
	/// [`Instruction::memory_size()`]: struct.Instruction.html#method.memory_size
	MemoryESDI = 21,
	/// `ES:[EDI]`. This operand kind uses [`Instruction::memory_size()`]
	///
	/// [`Instruction::memory_size()`]: struct.Instruction.html#method.memory_size
	MemoryESEDI = 22,
	/// `ES:[RDI]`. This operand kind uses [`Instruction::memory_size()`]
	///
	/// [`Instruction::memory_size()`]: struct.Instruction.html#method.memory_size
	MemoryESRDI = 23,
	/// 64-bit offset `[xxxxxxxxxxxxxxxx]`. This operand kind uses [`Instruction::memory_address64()`], [`Instruction::memory_segment()`], [`Instruction::segment_prefix()`], [`Instruction::memory_size()`]
	///
	/// [`Instruction::memory_address64()`]: struct.Instruction.html#method.memory_address64
	/// [`Instruction::memory_segment()`]: struct.Instruction.html#method.memory_segment
	/// [`Instruction::segment_prefix()`]: struct.Instruction.html#method.segment_prefix
	/// [`Instruction::memory_size()`]: struct.Instruction.html#method.memory_size
	Memory64 = 24,
	/// Memory operand.
	///
	/// This operand kind uses [`Instruction::memory_displ_size()`], [`Instruction::memory_size()`], [`Instruction::memory_index_scale()`], [`Instruction::memory_displacement()`], [`Instruction::memory_base()`], [`Instruction::memory_index()`], [`Instruction::memory_segment()`], [`Instruction::segment_prefix()`]
	///
	/// [`Instruction::memory_displ_size()`]: struct.Instruction.html#method.memory_displ_size
	/// [`Instruction::memory_size()`]: struct.Instruction.html#method.memory_size
	/// [`Instruction::memory_index_scale()`]: struct.Instruction.html#method.memory_index_scale
	/// [`Instruction::memory_displacement()`]: struct.Instruction.html#method.memory_displacement
	/// [`Instruction::memory_base()`]: struct.Instruction.html#method.memory_base
	/// [`Instruction::memory_index()`]: struct.Instruction.html#method.memory_index
	/// [`Instruction::memory_segment()`]: struct.Instruction.html#method.memory_segment
	/// [`Instruction::segment_prefix()`]: struct.Instruction.html#method.segment_prefix
	Memory = 25,
}
#[cfg_attr(feature = "cargo-fmt", rustfmt::skip)]
static GEN_DEBUG_OP_KIND: [&str; 26] = [
	"Register",
	"NearBranch16",
	"NearBranch32",
	"NearBranch64",
	"FarBranch16",
	"FarBranch32",
	"Immediate8",
	"Immediate8_2nd",
	"Immediate16",
	"Immediate32",
	"Immediate64",
	"Immediate8to16",
	"Immediate8to32",
	"Immediate8to64",
	"Immediate32to64",
	"MemorySegSI",
	"MemorySegESI",
	"MemorySegRSI",
	"MemorySegDI",
	"MemorySegEDI",
	"MemorySegRDI",
	"MemoryESDI",
	"MemoryESEDI",
	"MemoryESRDI",
	"Memory64",
	"Memory",
];
impl fmt::Debug for OpKind {
	#[inline]
	fn fmt<'a>(&self, f: &mut fmt::Formatter<'a>) -> fmt::Result {
		write!(f, "{}", GEN_DEBUG_OP_KIND[*self as usize])?;
		Ok(())
	}
}
impl Default for OpKind {
	#[cfg_attr(has_must_use, must_use)]
	#[inline]
	fn default() -> Self {
		OpKind::Register
	}
}
// GENERATOR-END: OpKind

// GENERATOR-BEGIN: VectorLength
// ⚠️This was generated by GENERATOR!🦹‍♂️
#[derive(Copy, Clone, Eq, PartialEq)]
#[cfg(any(feature = "decoder", feature = "encoder"))]
#[allow(dead_code)]
pub(crate) enum VectorLength {
	L128,
	L256,
	L512,
	Unknown,
}
#[cfg(any(feature = "decoder", feature = "encoder"))]
#[cfg_attr(feature = "cargo-fmt", rustfmt::skip)]
static GEN_DEBUG_VECTOR_LENGTH: [&str; 4] = [
	"L128",
	"L256",
	"L512",
	"Unknown",
];
#[cfg(any(feature = "decoder", feature = "encoder"))]
impl fmt::Debug for VectorLength {
	#[inline]
	fn fmt<'a>(&self, f: &mut fmt::Formatter<'a>) -> fmt::Result {
		write!(f, "{}", GEN_DEBUG_VECTOR_LENGTH[*self as usize])?;
		Ok(())
	}
}
#[cfg(any(feature = "decoder", feature = "encoder"))]
impl Default for VectorLength {
	#[cfg_attr(has_must_use, must_use)]
	#[inline]
	fn default() -> Self {
		VectorLength::L128
	}
}
// GENERATOR-END: VectorLength

// GENERATOR-BEGIN: MandatoryPrefixByte
// ⚠️This was generated by GENERATOR!🦹‍♂️
#[derive(Copy, Clone, Eq, PartialEq)]
#[cfg(any(feature = "decoder", feature = "encoder"))]
#[allow(dead_code)]
pub(crate) enum MandatoryPrefixByte {
	None,
	P66,
	PF3,
	PF2,
}
#[cfg(any(feature = "decoder", feature = "encoder"))]
#[cfg_attr(feature = "cargo-fmt", rustfmt::skip)]
static GEN_DEBUG_MANDATORY_PREFIX_BYTE: [&str; 4] = [
	"None",
	"P66",
	"PF3",
	"PF2",
];
#[cfg(any(feature = "decoder", feature = "encoder"))]
impl fmt::Debug for MandatoryPrefixByte {
	#[inline]
	fn fmt<'a>(&self, f: &mut fmt::Formatter<'a>) -> fmt::Result {
		write!(f, "{}", GEN_DEBUG_MANDATORY_PREFIX_BYTE[*self as usize])?;
		Ok(())
	}
}
#[cfg(any(feature = "decoder", feature = "encoder"))]
impl Default for MandatoryPrefixByte {
	#[cfg_attr(has_must_use, must_use)]
	#[inline]
	fn default() -> Self {
		MandatoryPrefixByte::None
	}
}
// GENERATOR-END: MandatoryPrefixByte

// GENERATOR-BEGIN: EncodingKind
// ⚠️This was generated by GENERATOR!🦹‍♂️
/// Instruction encoding
#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Hash)]
#[cfg_attr(all(not(feature = "exhaustive_enums"), has_non_exhaustive), non_exhaustive)]
#[cfg(any(feature = "decoder", feature = "encoder", feature = "instr_info"))]
pub enum EncodingKind {
	/// Legacy encoding
	Legacy = 0,
	/// VEX encoding
	VEX = 1,
	/// EVEX encoding
	EVEX = 2,
	/// XOP encoding
	XOP = 3,
	/// 3DNow! encoding
	D3NOW = 4,
}
#[cfg(any(feature = "decoder", feature = "encoder", feature = "instr_info"))]
#[cfg_attr(feature = "cargo-fmt", rustfmt::skip)]
static GEN_DEBUG_ENCODING_KIND: [&str; 5] = [
	"Legacy",
	"VEX",
	"EVEX",
	"XOP",
	"D3NOW",
];
#[cfg(any(feature = "decoder", feature = "encoder", feature = "instr_info"))]
impl fmt::Debug for EncodingKind {
	#[inline]
	fn fmt<'a>(&self, f: &mut fmt::Formatter<'a>) -> fmt::Result {
		write!(f, "{}", GEN_DEBUG_ENCODING_KIND[*self as usize])?;
		Ok(())
	}
}
#[cfg(any(feature = "decoder", feature = "encoder", feature = "instr_info"))]
impl Default for EncodingKind {
	#[cfg_attr(has_must_use, must_use)]
	#[inline]
	fn default() -> Self {
		EncodingKind::Legacy
	}
}
// GENERATOR-END: EncodingKind

// GENERATOR-BEGIN: TupleType
// ⚠️This was generated by GENERATOR!🦹‍♂️
/// Tuple type (EVEX) which can be used to get the disp8 scale factor `N`
#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Hash)]
#[cfg_attr(all(not(feature = "exhaustive_enums"), has_non_exhaustive), non_exhaustive)]
#[cfg(any(feature = "decoder", feature = "encoder"))]
#[allow(non_camel_case_types)]
pub enum TupleType {
	/// `N = 1`
	None = 0,
	/// `N = b ? (W ? 8 : 4) : 16`
	Full_128 = 1,
	/// `N = b ? (W ? 8 : 4) : 32`
	Full_256 = 2,
	/// `N = b ? (W ? 8 : 4) : 64`
	Full_512 = 3,
	/// `N = b ? 4 : 8`
	Half_128 = 4,
	/// `N = b ? 4 : 16`
	Half_256 = 5,
	/// `N = b ? 4 : 32`
	Half_512 = 6,
	/// `N = 16`
	Full_Mem_128 = 7,
	/// `N = 32`
	Full_Mem_256 = 8,
	/// `N = 64`
	Full_Mem_512 = 9,
	/// `N = W ? 8 : 4`
	Tuple1_Scalar = 10,
	/// `N = 1`
	Tuple1_Scalar_1 = 11,
	/// `N = 2`
	Tuple1_Scalar_2 = 12,
	/// `N = 4`
	Tuple1_Scalar_4 = 13,
	/// `N = 8`
	Tuple1_Scalar_8 = 14,
	/// `N = 4`
	Tuple1_Fixed_4 = 15,
	/// `N = 8`
	Tuple1_Fixed_8 = 16,
	/// `N = W ? 16 : 8`
	Tuple2 = 17,
	/// `N = W ? 32 : 16`
	Tuple4 = 18,
	/// `N = W ? error : 32`
	Tuple8 = 19,
	/// `N = 16`
	Tuple1_4X = 20,
	/// `N = 8`
	Half_Mem_128 = 21,
	/// `N = 16`
	Half_Mem_256 = 22,
	/// `N = 32`
	Half_Mem_512 = 23,
	/// `N = 4`
	Quarter_Mem_128 = 24,
	/// `N = 8`
	Quarter_Mem_256 = 25,
	/// `N = 16`
	Quarter_Mem_512 = 26,
	/// `N = 2`
	Eighth_Mem_128 = 27,
	/// `N = 4`
	Eighth_Mem_256 = 28,
	/// `N = 8`
	Eighth_Mem_512 = 29,
	/// `N = 16`
	Mem128 = 30,
	/// `N = 8`
	MOVDDUP_128 = 31,
	/// `N = 32`
	MOVDDUP_256 = 32,
	/// `N = 64`
	MOVDDUP_512 = 33,
}
#[cfg(any(feature = "decoder", feature = "encoder"))]
#[cfg_attr(feature = "cargo-fmt", rustfmt::skip)]
static GEN_DEBUG_TUPLE_TYPE: [&str; 34] = [
	"None",
	"Full_128",
	"Full_256",
	"Full_512",
	"Half_128",
	"Half_256",
	"Half_512",
	"Full_Mem_128",
	"Full_Mem_256",
	"Full_Mem_512",
	"Tuple1_Scalar",
	"Tuple1_Scalar_1",
	"Tuple1_Scalar_2",
	"Tuple1_Scalar_4",
	"Tuple1_Scalar_8",
	"Tuple1_Fixed_4",
	"Tuple1_Fixed_8",
	"Tuple2",
	"Tuple4",
	"Tuple8",
	"Tuple1_4X",
	"Half_Mem_128",
	"Half_Mem_256",
	"Half_Mem_512",
	"Quarter_Mem_128",
	"Quarter_Mem_256",
	"Quarter_Mem_512",
	"Eighth_Mem_128",
	"Eighth_Mem_256",
	"Eighth_Mem_512",
	"Mem128",
	"MOVDDUP_128",
	"MOVDDUP_256",
	"MOVDDUP_512",
];
#[cfg(any(feature = "decoder", feature = "encoder"))]
impl fmt::Debug for TupleType {
	#[inline]
	fn fmt<'a>(&self, f: &mut fmt::Formatter<'a>) -> fmt::Result {
		write!(f, "{}", GEN_DEBUG_TUPLE_TYPE[*self as usize])?;
		Ok(())
	}
}
#[cfg(any(feature = "decoder", feature = "encoder"))]
impl Default for TupleType {
	#[cfg_attr(has_must_use, must_use)]
	#[inline]
	fn default() -> Self {
		TupleType::None
	}
}
// GENERATOR-END: TupleType

// GENERATOR-BEGIN: FlowControl
// ⚠️This was generated by GENERATOR!🦹‍♂️
/// Flow control
#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Hash)]
#[cfg(feature = "instr_info")]
pub enum FlowControl {
	/// The next instruction that will be executed is the next instruction in the instruction stream
	Next = 0,
	/// It's an unconditional branch instruction: `JMP NEAR`, `JMP FAR`
	UnconditionalBranch = 1,
	/// It's an unconditional indirect branch: `JMP NEAR reg`, `JMP NEAR [mem]`, `JMP FAR [mem]`
	IndirectBranch = 2,
	/// It's a conditional branch instruction: `Jcc SHORT`, `Jcc NEAR`, `LOOP`, `LOOPcc`, `JRCXZ`
	ConditionalBranch = 3,
	/// It's a return instruction: `RET NEAR`, `RET FAR`, `IRET`, `SYSRET`, `SYSEXIT`, `RSM`, `VMLAUNCH`, `VMRESUME`, `VMRUN`, `SKINIT`
	Return = 4,
	/// It's a call instruction: `CALL NEAR`, `CALL FAR`, `SYSCALL`, `SYSENTER`, `VMCALL`, `VMMCALL`
	Call = 5,
	/// It's an indirect call instruction: `CALL NEAR reg`, `CALL NEAR [mem]`, `CALL FAR [mem]`
	IndirectCall = 6,
	/// It's an interrupt instruction: `INT n`, `INT3`, `INT1`, `INTO`
	Interrupt = 7,
	/// It's `XBEGIN`, `XABORT`, `XEND`, `XSUSLDTRK`, `XRESLDTRK`
	XbeginXabortXend = 8,
	/// It's an invalid instruction, eg. [`Code::INVALID`], `UD0`, `UD1`, `UD2`
	///
	/// [`Code::INVALID`]: enum.Code.html#variant.INVALID
	Exception = 9,
}
#[cfg(feature = "instr_info")]
#[cfg_attr(feature = "cargo-fmt", rustfmt::skip)]
static GEN_DEBUG_FLOW_CONTROL: [&str; 10] = [
	"Next",
	"UnconditionalBranch",
	"IndirectBranch",
	"ConditionalBranch",
	"Return",
	"Call",
	"IndirectCall",
	"Interrupt",
	"XbeginXabortXend",
	"Exception",
];
#[cfg(feature = "instr_info")]
impl fmt::Debug for FlowControl {
	#[inline]
	fn fmt<'a>(&self, f: &mut fmt::Formatter<'a>) -> fmt::Result {
		write!(f, "{}", GEN_DEBUG_FLOW_CONTROL[*self as usize])?;
		Ok(())
	}
}
#[cfg(feature = "instr_info")]
impl Default for FlowControl {
	#[cfg_attr(has_must_use, must_use)]
	#[inline]
	fn default() -> Self {
		FlowControl::Next
	}
}
// GENERATOR-END: FlowControl

// GENERATOR-BEGIN: OpCodeOperandKind
// ⚠️This was generated by GENERATOR!🦹‍♂️
/// Operand kind
#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Hash)]
#[cfg_attr(all(not(feature = "exhaustive_enums"), has_non_exhaustive), non_exhaustive)]
#[cfg(all(feature = "encoder", feature = "op_code_info"))]
#[allow(non_camel_case_types)]
pub enum OpCodeOperandKind {
	/// No operand
	None = 0,
	/// Far branch 16-bit offset, 16-bit segment/selector
	farbr2_2 = 1,
	/// Far branch 32-bit offset, 16-bit segment/selector
	farbr4_2 = 2,
	/// Memory offset without a modrm byte (eg. `MOV AL,[offset]`)
	mem_offs = 3,
	/// Memory (modrm)
	mem = 4,
	/// Memory (modrm), MPX:
	///
	/// 16/32-bit mode: must be 32-bit addressing
	///
	/// 64-bit mode: 64-bit addressing is forced
	mem_mpx = 5,
	/// Memory (modrm), MPX:
	///
	/// 16/32-bit mode: must be 32-bit addressing
	///
	/// 64-bit mode: 64-bit addressing is forced and must not be RIP relative
	mem_mib = 6,
	/// Memory (modrm), vsib32, xmm registers
	mem_vsib32x = 7,
	/// Memory (modrm), vsib64, xmm registers
	mem_vsib64x = 8,
	/// Memory (modrm), vsib32, ymm registers
	mem_vsib32y = 9,
	/// Memory (modrm), vsib64, ymm registers
	mem_vsib64y = 10,
	/// Memory (modrm), vsib32, zmm registers
	mem_vsib32z = 11,
	/// Memory (modrm), vsib64, zmm registers
	mem_vsib64z = 12,
	/// 8-bit GPR or memory
	r8_or_mem = 13,
	/// 16-bit GPR or memory
	r16_or_mem = 14,
	/// 32-bit GPR or memory
	r32_or_mem = 15,
	/// 32-bit GPR or memory, MPX: 16/32-bit mode: must be 32-bit addressing, 64-bit mode: 64-bit addressing is forced
	r32_or_mem_mpx = 16,
	/// 64-bit GPR or memory
	r64_or_mem = 17,
	/// 64-bit GPR or memory, MPX: 16/32-bit mode: must be 32-bit addressing, 64-bit mode: 64-bit addressing is forced
	r64_or_mem_mpx = 18,
	/// MM register or memory
	mm_or_mem = 19,
	/// XMM register or memory
	xmm_or_mem = 20,
	/// YMM register or memory
	ymm_or_mem = 21,
	/// ZMM register or memory
	zmm_or_mem = 22,
	/// BND register or memory, MPX: 16/32-bit mode: must be 32-bit addressing, 64-bit mode: 64-bit addressing is forced
	bnd_or_mem_mpx = 23,
	/// K register or memory
	k_or_mem = 24,
	/// 8-bit GPR encoded in the `reg` field of the modrm byte
	r8_reg = 25,
	/// 8-bit GPR encoded in the low 3 bits of the opcode
	r8_opcode = 26,
	/// 16-bit GPR encoded in the `reg` field of the modrm byte
	r16_reg = 27,
	/// 16-bit GPR encoded in the `reg` field of the modrm byte. This is a memory operand and it uses the address size prefix (`67h`) not the operand size prefix (`66h`).
	r16_reg_mem = 28,
	/// 16-bit GPR encoded in the `mod + r/m` fields of the modrm byte
	r16_rm = 29,
	/// 16-bit GPR encoded in the low 3 bits of the opcode
	r16_opcode = 30,
	/// 32-bit GPR encoded in the `reg` field of the modrm byte
	r32_reg = 31,
	/// 32-bit GPR encoded in the `reg` field of the modrm byte. This is a memory operand and it uses the address size prefix (`67h`) not the operand size prefix (`66h`).
	r32_reg_mem = 32,
	/// 32-bit GPR encoded in the `mod + r/m` fields of the modrm byte
	r32_rm = 33,
	/// 32-bit GPR encoded in the low 3 bits of the opcode
	r32_opcode = 34,
	/// 32-bit GPR encoded in the the `V'vvvv` field (VEX/EVEX/XOP)
	r32_vvvv = 35,
	/// 64-bit GPR encoded in the `reg` field of the modrm byte
	r64_reg = 36,
	/// 64-bit GPR encoded in the `reg` field of the modrm byte. This is a memory operand and it uses the address size prefix (`67h`) not the operand size prefix (`66h`).
	r64_reg_mem = 37,
	/// 64-bit GPR encoded in the `mod + r/m` fields of the modrm byte
	r64_rm = 38,
	/// 64-bit GPR encoded in the low 3 bits of the opcode
	r64_opcode = 39,
	/// 64-bit GPR encoded in the the `V'vvvv` field (VEX/EVEX/XOP)
	r64_vvvv = 40,
	/// Segment register encoded in the `reg` field of the modrm byte
	seg_reg = 41,
	/// K register encoded in the `reg` field of the modrm byte
	k_reg = 42,
	/// K register (+1) encoded in the `reg` field of the modrm byte
	kp1_reg = 43,
	/// K register encoded in the `mod + r/m` fields of the modrm byte
	k_rm = 44,
	/// K register encoded in the the `V'vvvv` field (VEX/EVEX/XOP)
	k_vvvv = 45,
	/// MM register encoded in the `reg` field of the modrm byte
	mm_reg = 46,
	/// MM register encoded in the `mod + r/m` fields of the modrm byte
	mm_rm = 47,
	/// XMM register encoded in the `reg` field of the modrm byte
	xmm_reg = 48,
	/// XMM register encoded in the `mod + r/m` fields of the modrm byte
	xmm_rm = 49,
	/// XMM register encoded in the the `V'vvvv` field (VEX/EVEX/XOP)
	xmm_vvvv = 50,
	/// XMM register (+3) encoded in the the `V'vvvv` field (VEX/EVEX/XOP)
	xmmp3_vvvv = 51,
	/// XMM register encoded in the the high 4 bits of the last 8-bit immediate (VEX/XOP only so only XMM0-XMM15)
	xmm_is4 = 52,
	/// XMM register encoded in the the high 4 bits of the last 8-bit immediate (VEX/XOP only so only XMM0-XMM15)
	xmm_is5 = 53,
	/// YMM register encoded in the `reg` field of the modrm byte
	ymm_reg = 54,
	/// YMM register encoded in the `mod + r/m` fields of the modrm byte
	ymm_rm = 55,
	/// YMM register encoded in the the `V'vvvv` field (VEX/EVEX/XOP)
	ymm_vvvv = 56,
	/// YMM register encoded in the the high 4 bits of the last 8-bit immediate (VEX/XOP only so only YMM0-YMM15)
	ymm_is4 = 57,
	/// YMM register encoded in the the high 4 bits of the last 8-bit immediate (VEX/XOP only so only YMM0-YMM15)
	ymm_is5 = 58,
	/// ZMM register encoded in the `reg` field of the modrm byte
	zmm_reg = 59,
	/// ZMM register encoded in the `mod + r/m` fields of the modrm byte
	zmm_rm = 60,
	/// ZMM register encoded in the the `V'vvvv` field (VEX/EVEX/XOP)
	zmm_vvvv = 61,
	/// ZMM register (+3) encoded in the the `V'vvvv` field (VEX/EVEX/XOP)
	zmmp3_vvvv = 62,
	/// CR register encoded in the `reg` field of the modrm byte
	cr_reg = 63,
	/// DR register encoded in the `reg` field of the modrm byte
	dr_reg = 64,
	/// TR register encoded in the `reg` field of the modrm byte
	tr_reg = 65,
	/// BND register encoded in the `reg` field of the modrm byte
	bnd_reg = 66,
	/// ES register
	es = 67,
	/// CS register
	cs = 68,
	/// SS register
	ss = 69,
	/// DS register
	ds = 70,
	/// FS register
	fs = 71,
	/// GS register
	gs = 72,
	/// AL register
	al = 73,
	/// CL register
	cl = 74,
	/// AX register
	ax = 75,
	/// DX register
	dx = 76,
	/// EAX register
	eax = 77,
	/// RAX register
	rax = 78,
	/// ST0 register
	st0 = 79,
	/// ST(i) register encoded in the low 3 bits of the opcode
	sti_opcode = 80,
	/// 2-bit immediate (m2z field, low 2 bits of the /is5 immediate, eg. `VPERMIL2PS`)
	imm2_m2z = 81,
	/// 8-bit immediate
	imm8 = 82,
	/// Constant 1 (8-bit immediate)
	imm8_const_1 = 83,
	/// 8-bit immediate sign extended to 16 bits
	imm8sex16 = 84,
	/// 8-bit immediate sign extended to 32 bits
	imm8sex32 = 85,
	/// 8-bit immediate sign extended to 64 bits
	imm8sex64 = 86,
	/// 16-bit immediate
	imm16 = 87,
	/// 32-bit immediate
	imm32 = 88,
	/// 32-bit immediate sign extended to 64 bits
	imm32sex64 = 89,
	/// 64-bit immediate
	imm64 = 90,
	/// `seg:[rSI]` memory operand (string instructions)
	seg_rSI = 91,
	/// `es:[rDI]` memory operand (string instructions)
	es_rDI = 92,
	/// `seg:[rDI]` memory operand (`(V)MASKMOVQ` instructions)
	seg_rDI = 93,
	/// `seg:[rBX+al]` memory operand (`XLATB` instruction)
	seg_rBX_al = 94,
	/// 16-bit branch, 1-byte signed relative offset
	br16_1 = 95,
	/// 32-bit branch, 1-byte signed relative offset
	br32_1 = 96,
	/// 64-bit branch, 1-byte signed relative offset
	br64_1 = 97,
	/// 16-bit branch, 2-byte signed relative offset
	br16_2 = 98,
	/// 32-bit branch, 4-byte signed relative offset
	br32_4 = 99,
	/// 64-bit branch, 4-byte signed relative offset
	br64_4 = 100,
	/// `XBEGIN`, 2-byte signed relative offset
	xbegin_2 = 101,
	/// `XBEGIN`, 4-byte signed relative offset
	xbegin_4 = 102,
	/// 2-byte branch offset (`JMPE` instruction)
	brdisp_2 = 103,
	/// 4-byte branch offset (`JMPE` instruction)
	brdisp_4 = 104,
}
#[cfg(all(feature = "encoder", feature = "op_code_info"))]
#[cfg_attr(feature = "cargo-fmt", rustfmt::skip)]
static GEN_DEBUG_OP_CODE_OPERAND_KIND: [&str; 105] = [
	"None",
	"farbr2_2",
	"farbr4_2",
	"mem_offs",
	"mem",
	"mem_mpx",
	"mem_mib",
	"mem_vsib32x",
	"mem_vsib64x",
	"mem_vsib32y",
	"mem_vsib64y",
	"mem_vsib32z",
	"mem_vsib64z",
	"r8_or_mem",
	"r16_or_mem",
	"r32_or_mem",
	"r32_or_mem_mpx",
	"r64_or_mem",
	"r64_or_mem_mpx",
	"mm_or_mem",
	"xmm_or_mem",
	"ymm_or_mem",
	"zmm_or_mem",
	"bnd_or_mem_mpx",
	"k_or_mem",
	"r8_reg",
	"r8_opcode",
	"r16_reg",
	"r16_reg_mem",
	"r16_rm",
	"r16_opcode",
	"r32_reg",
	"r32_reg_mem",
	"r32_rm",
	"r32_opcode",
	"r32_vvvv",
	"r64_reg",
	"r64_reg_mem",
	"r64_rm",
	"r64_opcode",
	"r64_vvvv",
	"seg_reg",
	"k_reg",
	"kp1_reg",
	"k_rm",
	"k_vvvv",
	"mm_reg",
	"mm_rm",
	"xmm_reg",
	"xmm_rm",
	"xmm_vvvv",
	"xmmp3_vvvv",
	"xmm_is4",
	"xmm_is5",
	"ymm_reg",
	"ymm_rm",
	"ymm_vvvv",
	"ymm_is4",
	"ymm_is5",
	"zmm_reg",
	"zmm_rm",
	"zmm_vvvv",
	"zmmp3_vvvv",
	"cr_reg",
	"dr_reg",
	"tr_reg",
	"bnd_reg",
	"es",
	"cs",
	"ss",
	"ds",
	"fs",
	"gs",
	"al",
	"cl",
	"ax",
	"dx",
	"eax",
	"rax",
	"st0",
	"sti_opcode",
	"imm2_m2z",
	"imm8",
	"imm8_const_1",
	"imm8sex16",
	"imm8sex32",
	"imm8sex64",
	"imm16",
	"imm32",
	"imm32sex64",
	"imm64",
	"seg_rSI",
	"es_rDI",
	"seg_rDI",
	"seg_rBX_al",
	"br16_1",
	"br32_1",
	"br64_1",
	"br16_2",
	"br32_4",
	"br64_4",
	"xbegin_2",
	"xbegin_4",
	"brdisp_2",
	"brdisp_4",
];
#[cfg(all(feature = "encoder", feature = "op_code_info"))]
impl fmt::Debug for OpCodeOperandKind {
	#[inline]
	fn fmt<'a>(&self, f: &mut fmt::Formatter<'a>) -> fmt::Result {
		write!(f, "{}", GEN_DEBUG_OP_CODE_OPERAND_KIND[*self as usize])?;
		Ok(())
	}
}
#[cfg(all(feature = "encoder", feature = "op_code_info"))]
impl Default for OpCodeOperandKind {
	#[cfg_attr(has_must_use, must_use)]
	#[inline]
	fn default() -> Self {
		OpCodeOperandKind::None
	}
}
// GENERATOR-END: OpCodeOperandKind

// GENERATOR-BEGIN: CpuidFeature
// ⚠️This was generated by GENERATOR!🦹‍♂️
/// `CPUID` feature flags
#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Hash)]
#[cfg_attr(all(not(feature = "exhaustive_enums"), has_non_exhaustive), non_exhaustive)]
#[cfg(feature = "instr_info")]
#[allow(non_camel_case_types)]
pub enum CpuidFeature {
	/// 8086 or later
	INTEL8086 = 0,
	/// 8086 only
	INTEL8086_ONLY = 1,
	/// 80186 or later
	INTEL186 = 2,
	/// 80286 or later
	INTEL286 = 3,
	/// 80286 only
	INTEL286_ONLY = 4,
	/// 80386 or later
	INTEL386 = 5,
	/// 80386 only
	INTEL386_ONLY = 6,
	/// 80386 A0-B0 stepping only (`XBTS`, `IBTS` instructions)
	INTEL386_A0_ONLY = 7,
	/// Intel486 or later
	INTEL486 = 8,
	/// Intel486 A stepping only (`CMPXCHG`)
	INTEL486_A_ONLY = 9,
	/// 80386 and Intel486 only
	INTEL386_486_ONLY = 10,
	/// IA-64
	IA64 = 11,
	/// CPUID.80000001H:EDX.LM\[bit 29\]
	X64 = 12,
	/// CPUID.(EAX=07H, ECX=0H):EBX.ADX\[bit 19\]
	ADX = 13,
	/// CPUID.01H:ECX.AES\[bit 25\]
	AES = 14,
	/// CPUID.01H:ECX.AVX\[bit 28\]
	AVX = 15,
	/// CPUID.(EAX=07H, ECX=0H):EBX.AVX2\[bit 5\]
	AVX2 = 16,
	/// CPUID.(EAX=07H, ECX=0H):EDX.AVX512_4FMAPS\[bit 3\]
	AVX512_4FMAPS = 17,
	/// CPUID.(EAX=07H, ECX=0H):EDX.AVX512_4VNNIW\[bit 2\]
	AVX512_4VNNIW = 18,
	/// CPUID.(EAX=07H, ECX=1H):EAX\[bit 5\]
	AVX512_BF16 = 19,
	/// CPUID.(EAX=07H, ECX=0H):ECX.AVX512_BITALG\[bit 12\]
	AVX512_BITALG = 20,
	/// CPUID.(EAX=07H, ECX=0H):EBX.AVX512_IFMA\[bit 21\]
	AVX512_IFMA = 21,
	/// CPUID.(EAX=07H, ECX=0H):ECX.AVX512_VBMI\[bit 1\]
	AVX512_VBMI = 22,
	/// CPUID.(EAX=07H, ECX=0H):ECX.AVX512_VBMI2\[bit 6\]
	AVX512_VBMI2 = 23,
	/// CPUID.(EAX=07H, ECX=0H):ECX.AVX512_VNNI\[bit 11\]
	AVX512_VNNI = 24,
	/// CPUID.(EAX=07H, ECX=0H):EDX\[bit 08\]
	AVX512_VP2INTERSECT = 25,
	/// CPUID.(EAX=07H, ECX=0H):ECX.AVX512_VPOPCNTDQ\[bit 14\]
	AVX512_VPOPCNTDQ = 26,
	/// CPUID.(EAX=07H, ECX=0H):EBX.AVX512BW\[bit 30\]
	AVX512BW = 27,
	/// CPUID.(EAX=07H, ECX=0H):EBX.AVX512CD\[bit 28\]
	AVX512CD = 28,
	/// CPUID.(EAX=07H, ECX=0H):EBX.AVX512DQ\[bit 17\]
	AVX512DQ = 29,
	/// CPUID.(EAX=07H, ECX=0H):EBX.AVX512ER\[bit 27\]
	AVX512ER = 30,
	/// CPUID.(EAX=07H, ECX=0H):EBX.AVX512F\[bit 16\]
	AVX512F = 31,
	/// CPUID.(EAX=07H, ECX=0H):EBX.AVX512PF\[bit 26\]
	AVX512PF = 32,
	/// CPUID.(EAX=07H, ECX=0H):EBX.AVX512VL\[bit 31\]
	AVX512VL = 33,
	/// CPUID.(EAX=07H, ECX=0H):EBX.BMI1\[bit 3\]
	BMI1 = 34,
	/// CPUID.(EAX=07H, ECX=0H):EBX.BMI2\[bit 8\]
	BMI2 = 35,
	/// CPUID.(EAX=07H, ECX=0H):EDX.CET_IBT\[bit 20\]
	CET_IBT = 36,
	/// CPUID.(EAX=07H, ECX=0H):ECX.CET_SS\[bit 7\]
	CET_SS = 37,
	/// `CL1INVMB` instruction (Intel SCC = Single-Chip Computer)
	CL1INVMB = 38,
	/// CPUID.(EAX=07H, ECX=0H):ECX.CLDEMOTE\[bit 25\]
	CLDEMOTE = 39,
	/// CPUID.(EAX=07H, ECX=0H):EBX.CLFLUSHOPT\[bit 23\]
	CLFLUSHOPT = 40,
	/// CPUID.01H:EDX.CLFSH\[bit 19\]
	CLFSH = 41,
	/// CPUID.(EAX=07H, ECX=0H):EBX.CLWB\[bit 24\]
	CLWB = 42,
	/// CPUID.80000008H:EBX.CLZERO\[bit 0\]
	CLZERO = 43,
	/// CPUID.01H:EDX.CMOV\[bit 15\]
	CMOV = 44,
	/// CPUID.01H:ECX.CMPXCHG16B\[bit 13\]
	CMPXCHG16B = 45,
	/// `RFLAGS.ID` can be toggled
	CPUID = 46,
	/// CPUID.01H:EDX.CX8\[bit 8\]
	CX8 = 47,
	/// CPUID.80000001H:EDX.3DNOW\[bit 31\]
	D3NOW = 48,
	/// CPUID.80000001H:EDX.3DNOWEXT\[bit 30\]
	D3NOWEXT = 49,
	/// CPUID.(EAX=12H, ECX=0H):EAX.OSS\[bit 5\]
	ENCLV = 50,
	/// CPUID.(EAX=07H, ECX=0H):ECX\[bit 29\]
	ENQCMD = 51,
	/// CPUID.01H:ECX.F16C\[bit 29\]
	F16C = 52,
	/// CPUID.01H:ECX.FMA\[bit 12\]
	FMA = 53,
	/// CPUID.80000001H:ECX.FMA4\[bit 16\]
	FMA4 = 54,
	/// 8087 or later (CPUID.01H:EDX.FPU\[bit 0\])
	FPU = 55,
	/// 80287 or later
	FPU287 = 56,
	/// 80287XL only
	FPU287XL_ONLY = 57,
	/// 80387 or later
	FPU387 = 58,
	/// 80387SL only
	FPU387SL_ONLY = 59,
	/// CPUID.(EAX=07H, ECX=0H):EBX.FSGSBASE\[bit 0\]
	FSGSBASE = 60,
	/// CPUID.01H:EDX.FXSR\[bit 24\]
	FXSR = 61,
	/// AMD Geode LX/GX CPU
	GEODE = 62,
	/// CPUID.(EAX=07H, ECX=0H):ECX.GFNI\[bit 8\]
	GFNI = 63,
	/// CPUID.(EAX=07H, ECX=0H):EBX.HLE\[bit 4\]
	HLE = 64,
	/// [`HLE`] or [`RTM`]
	///
	/// [`HLE`]: enum.CpuidFeature.html#variant.HLE
	/// [`RTM`]: enum.CpuidFeature.html#variant.RTM
	HLE_or_RTM = 65,
	/// [`VMX`] and IA32_VMX_EPT_VPID_CAP\[bit 20\]
	///
	/// [`VMX`]: enum.CpuidFeature.html#variant.VMX
	INVEPT = 66,
	/// CPUID.(EAX=07H, ECX=0H):EBX.INVPCID\[bit 10\]
	INVPCID = 67,
	/// [`VMX`] and IA32_VMX_EPT_VPID_CAP\[bit 32\]
	///
	/// [`VMX`]: enum.CpuidFeature.html#variant.VMX
	INVVPID = 68,
	/// CPUID.80000001H:ECX.LWP\[bit 15\]
	LWP = 69,
	/// CPUID.80000001H:ECX.LZCNT\[bit 5\]
	LZCNT = 70,
	/// CPUID.80000008H:EBX.MCOMMIT\[bit 8\]
	MCOMMIT = 71,
	/// CPUID.01H:EDX.MMX\[bit 23\]
	MMX = 72,
	/// CPUID.01H:ECX.MONITOR\[bit 3\]
	MONITOR = 73,
	/// CPUID.80000001H:ECX.MONITORX\[bit 29\]
	MONITORX = 74,
	/// CPUID.01H:ECX.MOVBE\[bit 22\]
	MOVBE = 75,
	/// CPUID.(EAX=07H, ECX=0H):ECX.MOVDIR64B\[bit 28\]
	MOVDIR64B = 76,
	/// CPUID.(EAX=07H, ECX=0H):ECX.MOVDIRI\[bit 27\]
	MOVDIRI = 77,
	/// CPUID.(EAX=07H, ECX=0H):EBX.MPX\[bit 14\]
	MPX = 78,
	/// CPUID.01H:EDX.MSR\[bit 5\]
	MSR = 79,
	/// Multi-byte nops (`0F1F /0`): CPUID.01H.EAX\[Bits 11:8\] = 0110B or 1111B
	MULTIBYTENOP = 80,
	/// CPUID.0C0000000H:EAX >= 0C0000001H AND CPUID.0C0000001H:EDX.ACE\[Bits 7:6\] = 11B (\[6\] = exists, \[7\] = enabled)
	PADLOCK_ACE = 81,
	/// CPUID.0C0000000H:EAX >= 0C0000001H AND CPUID.0C0000001H:EDX.PHE\[Bits 11:10\] = 11B (\[10\] = exists, \[11\] = enabled)
	PADLOCK_PHE = 82,
	/// CPUID.0C0000000H:EAX >= 0C0000001H AND CPUID.0C0000001H:EDX.PMM\[Bits 13:12\] = 11B (\[12\] = exists, \[13\] = enabled)
	PADLOCK_PMM = 83,
	/// CPUID.0C0000000H:EAX >= 0C0000001H AND CPUID.0C0000001H:EDX.RNG\[Bits 3:2\] = 11B (\[2\] = exists, \[3\] = enabled)
	PADLOCK_RNG = 84,
	/// `PAUSE` instruction (Pentium 4 or later)
	PAUSE = 85,
	/// CPUID.01H:ECX.PCLMULQDQ\[bit 1\]
	PCLMULQDQ = 86,
	/// CPUID.(EAX=07H, ECX=0H):EBX.PCOMMIT\[bit 22\]
	PCOMMIT = 87,
	/// CPUID.(EAX=07H, ECX=0H):EDX.PCONFIG\[bit 18\]
	PCONFIG = 88,
	/// CPUID.(EAX=07H, ECX=0H):ECX.PKU\[bit 3\]
	PKU = 89,
	/// CPUID.01H:ECX.POPCNT\[bit 23\]
	POPCNT = 90,
	/// CPUID.80000001H:ECX.PREFETCHW\[bit 8\]
	PREFETCHW = 91,
	/// CPUID.(EAX=07H, ECX=0H):ECX.PREFETCHWT1\[bit 0\]
	PREFETCHWT1 = 92,
	/// CPUID.(EAX=14H, ECX=0H):EBX.PTWRITE\[bit 4\]
	PTWRITE = 93,
	/// CPUID.(EAX=07H, ECX=0H):ECX.RDPID\[bit 22\]
	RDPID = 94,
	/// `RDPMC` instruction (Pentium MMX or later, or Pentium Pro or later)
	RDPMC = 95,
	/// CPUID.80000008H:EBX.RDPRU\[bit 4\]
	RDPRU = 96,
	/// CPUID.01H:ECX.RDRAND\[bit 30\]
	RDRAND = 97,
	/// CPUID.(EAX=07H, ECX=0H):EBX.RDSEED\[bit 18\]
	RDSEED = 98,
	/// CPUID.80000001H:EDX.RDTSCP\[bit 27\]
	RDTSCP = 99,
	/// CPUID.(EAX=07H, ECX=0H):EBX.RTM\[bit 11\]
	RTM = 100,
	/// CPUID.01H:EDX.SEP\[bit 11\]
	SEP = 101,
	/// CPUID.(EAX=12H, ECX=0H):EAX.SGX1\[bit 0\]
	SGX1 = 102,
	/// CPUID.(EAX=07H, ECX=0H):EBX.SHA\[bit 29\]
	SHA = 103,
	/// CPUID.80000001H:ECX.SKINIT\[bit 12\]
	SKINIT = 104,
	/// [`SKINIT`] or [`SVML`]
	///
	/// [`SKINIT`]: enum.CpuidFeature.html#variant.SKINIT
	/// [`SVML`]: enum.CpuidFeature.html#variant.SVML
	SKINIT_or_SVML = 105,
	/// CPUID.(EAX=07H, ECX=0H):EBX.SMAP\[bit 20\]
	SMAP = 106,
	/// CPUID.01H:ECX.SMX\[bit 6\]
	SMX = 107,
	/// CPUID.01H:EDX.SSE\[bit 25\]
	SSE = 108,
	/// CPUID.01H:EDX.SSE2\[bit 26\]
	SSE2 = 109,
	/// CPUID.01H:ECX.SSE3\[bit 0\]
	SSE3 = 110,
	/// CPUID.01H:ECX.SSE4_1\[bit 19\]
	SSE4_1 = 111,
	/// CPUID.01H:ECX.SSE4_2\[bit 20\]
	SSE4_2 = 112,
	/// CPUID.80000001H:ECX.SSE4A\[bit 6\]
	SSE4A = 113,
	/// CPUID.01H:ECX.SSSE3\[bit 9\]
	SSSE3 = 114,
	/// CPUID.80000001H:ECX.SVM\[bit 2\]
	SVM = 115,
	/// CPUID.8000000AH:EDX.SVML\[bit 2\]
	SVML = 116,
	/// CPUID.80000001H:EDX.SYSCALL\[bit 11\]
	SYSCALL = 117,
	/// CPUID.80000001H:ECX.TBM\[bit 21\]
	TBM = 118,
	/// CPUID.01H:EDX.TSC\[bit 4\]
	TSC = 119,
	/// CPUID.(EAX=07H, ECX=0H):ECX.VAES\[bit 9\]
	VAES = 120,
	/// CPUID.01H:ECX.VMX\[bit 5\]
	VMX = 121,
	/// CPUID.(EAX=07H, ECX=0H):ECX.VPCLMULQDQ\[bit 10\]
	VPCLMULQDQ = 122,
	/// CPUID.(EAX=07H, ECX=0H):ECX.WAITPKG\[bit 5\]
	WAITPKG = 123,
	/// CPUID.(EAX=80000008H, ECX=0H):EBX.WBNOINVD\[bit 9\]
	WBNOINVD = 124,
	/// CPUID.80000001H:ECX.XOP\[bit 11\]
	XOP = 125,
	/// CPUID.01H:ECX.XSAVE\[bit 26\]
	XSAVE = 126,
	/// CPUID.(EAX=0DH, ECX=1H):EAX.XSAVEC\[bit 1\]
	XSAVEC = 127,
	/// CPUID.(EAX=0DH, ECX=1H):EAX.XSAVEOPT\[bit 0\]
	XSAVEOPT = 128,
	/// CPUID.(EAX=0DH, ECX=1H):EAX.XSAVES\[bit 3\]
	XSAVES = 129,
	/// CPUID.8000001FH:EAX.SNP\[bit 4\]
	SNP = 130,
	/// CPUID.(EAX=07H, ECX=0H):EDX.SERIALIZE\[bit 14\]
	SERIALIZE = 131,
	/// CPUID.(EAX=07H, ECX=0H):EDX.TSXLDTRK\[bit 16\]
	TSXLDTRK = 132,
	/// CPUID.80000001H:EDX.INVLPGB\[bit ??\]
	INVLPGB = 133,
}
#[cfg(feature = "instr_info")]
#[cfg_attr(feature = "cargo-fmt", rustfmt::skip)]
static GEN_DEBUG_CPUID_FEATURE: [&str; 134] = [
	"INTEL8086",
	"INTEL8086_ONLY",
	"INTEL186",
	"INTEL286",
	"INTEL286_ONLY",
	"INTEL386",
	"INTEL386_ONLY",
	"INTEL386_A0_ONLY",
	"INTEL486",
	"INTEL486_A_ONLY",
	"INTEL386_486_ONLY",
	"IA64",
	"X64",
	"ADX",
	"AES",
	"AVX",
	"AVX2",
	"AVX512_4FMAPS",
	"AVX512_4VNNIW",
	"AVX512_BF16",
	"AVX512_BITALG",
	"AVX512_IFMA",
	"AVX512_VBMI",
	"AVX512_VBMI2",
	"AVX512_VNNI",
	"AVX512_VP2INTERSECT",
	"AVX512_VPOPCNTDQ",
	"AVX512BW",
	"AVX512CD",
	"AVX512DQ",
	"AVX512ER",
	"AVX512F",
	"AVX512PF",
	"AVX512VL",
	"BMI1",
	"BMI2",
	"CET_IBT",
	"CET_SS",
	"CL1INVMB",
	"CLDEMOTE",
	"CLFLUSHOPT",
	"CLFSH",
	"CLWB",
	"CLZERO",
	"CMOV",
	"CMPXCHG16B",
	"CPUID",
	"CX8",
	"D3NOW",
	"D3NOWEXT",
	"ENCLV",
	"ENQCMD",
	"F16C",
	"FMA",
	"FMA4",
	"FPU",
	"FPU287",
	"FPU287XL_ONLY",
	"FPU387",
	"FPU387SL_ONLY",
	"FSGSBASE",
	"FXSR",
	"GEODE",
	"GFNI",
	"HLE",
	"HLE_or_RTM",
	"INVEPT",
	"INVPCID",
	"INVVPID",
	"LWP",
	"LZCNT",
	"MCOMMIT",
	"MMX",
	"MONITOR",
	"MONITORX",
	"MOVBE",
	"MOVDIR64B",
	"MOVDIRI",
	"MPX",
	"MSR",
	"MULTIBYTENOP",
	"PADLOCK_ACE",
	"PADLOCK_PHE",
	"PADLOCK_PMM",
	"PADLOCK_RNG",
	"PAUSE",
	"PCLMULQDQ",
	"PCOMMIT",
	"PCONFIG",
	"PKU",
	"POPCNT",
	"PREFETCHW",
	"PREFETCHWT1",
	"PTWRITE",
	"RDPID",
	"RDPMC",
	"RDPRU",
	"RDRAND",
	"RDSEED",
	"RDTSCP",
	"RTM",
	"SEP",
	"SGX1",
	"SHA",
	"SKINIT",
	"SKINIT_or_SVML",
	"SMAP",
	"SMX",
	"SSE",
	"SSE2",
	"SSE3",
	"SSE4_1",
	"SSE4_2",
	"SSE4A",
	"SSSE3",
	"SVM",
	"SVML",
	"SYSCALL",
	"TBM",
	"TSC",
	"VAES",
	"VMX",
	"VPCLMULQDQ",
	"WAITPKG",
	"WBNOINVD",
	"XOP",
	"XSAVE",
	"XSAVEC",
	"XSAVEOPT",
	"XSAVES",
	"SNP",
	"SERIALIZE",
	"TSXLDTRK",
	"INVLPGB",
];
#[cfg(feature = "instr_info")]
impl fmt::Debug for CpuidFeature {
	#[inline]
	fn fmt<'a>(&self, f: &mut fmt::Formatter<'a>) -> fmt::Result {
		write!(f, "{}", GEN_DEBUG_CPUID_FEATURE[*self as usize])?;
		Ok(())
	}
}
#[cfg(feature = "instr_info")]
impl Default for CpuidFeature {
	#[cfg_attr(has_must_use, must_use)]
	#[inline]
	fn default() -> Self {
		CpuidFeature::INTEL8086
	}
}
// GENERATOR-END: CpuidFeature

// GENERATOR-BEGIN: RflagsBits
// ⚠️This was generated by GENERATOR!🦹‍♂️
/// `RFLAGS` bits supported by the instruction info code
#[allow(missing_copy_implementations)]
#[allow(missing_debug_implementations)]
#[cfg(feature = "instr_info")]
pub struct RflagsBits;
#[allow(missing_docs)]
#[cfg(feature = "instr_info")]
impl RflagsBits {
	pub const NONE: u32 = 0x0000_0000;
	pub const OF: u32 = 0x0000_0001;
	pub const SF: u32 = 0x0000_0002;
	pub const ZF: u32 = 0x0000_0004;
	pub const AF: u32 = 0x0000_0008;
	pub const CF: u32 = 0x0000_0010;
	pub const PF: u32 = 0x0000_0020;
	pub const DF: u32 = 0x0000_0040;
	pub const IF: u32 = 0x0000_0080;
	pub const AC: u32 = 0x0000_0100;
}
// GENERATOR-END: RflagsBits

// GENERATOR-BEGIN: OpAccess
// ⚠️This was generated by GENERATOR!🦹‍♂️
/// Operand, register and memory access
#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Hash)]
#[cfg(feature = "instr_info")]
pub enum OpAccess {
	/// Nothing is read and nothing is written
	None = 0,
	/// The value is read
	Read = 1,
	/// The value is sometimes read and sometimes not
	CondRead = 2,
	/// The value is completely overwritten
	Write = 3,
	/// Conditional write, sometimes it's written and sometimes it's not modified
	CondWrite = 4,
	/// The value is read and written
	ReadWrite = 5,
	/// The value is read and sometimes written
	ReadCondWrite = 6,
	/// The memory operand doesn't refer to memory (eg. `LEA` instruction) or it's an instruction that doesn't read the data to a register or doesn't write to the memory location, it just prefetches/invalidates it, eg. `INVLPG`, `PREFETCHNTA`, `VGATHERPF0DPS`, etc.
	NoMemAccess = 7,
}
#[cfg(feature = "instr_info")]
#[cfg_attr(feature = "cargo-fmt", rustfmt::skip)]
static GEN_DEBUG_OP_ACCESS: [&str; 8] = [
	"None",
	"Read",
	"CondRead",
	"Write",
	"CondWrite",
	"ReadWrite",
	"ReadCondWrite",
	"NoMemAccess",
];
#[cfg(feature = "instr_info")]
impl fmt::Debug for OpAccess {
	#[inline]
	fn fmt<'a>(&self, f: &mut fmt::Formatter<'a>) -> fmt::Result {
		write!(f, "{}", GEN_DEBUG_OP_ACCESS[*self as usize])?;
		Ok(())
	}
}
#[cfg(feature = "instr_info")]
impl Default for OpAccess {
	#[cfg_attr(has_must_use, must_use)]
	#[inline]
	fn default() -> Self {
		OpAccess::None
	}
}
// GENERATOR-END: OpAccess

// GENERATOR-BEGIN: ConditionCode
// ⚠️This was generated by GENERATOR!🦹‍♂️
/// Instruction condition code (used by `Jcc`, `SETcc`, `CMOVcc`, `LOOPcc`)
#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Hash)]
#[cfg(feature = "instr_info")]
#[allow(non_camel_case_types)]
pub enum ConditionCode {
	/// The instruction doesn't have a condition code
	None = 0,
	/// Overflow (`OF=1`)
	o = 1,
	/// Not overflow (`OF=0`)
	no = 2,
	/// Below (unsigned) (`CF=1`)
	b = 3,
	/// Above or equal (unsigned) (`CF=0`)
	ae = 4,
	/// Equal / zero (`ZF=1`)
	e = 5,
	/// Not equal / zero (`ZF=0`)
	ne = 6,
	/// Below or equal (unsigned) (`CF=1 or ZF=1`)
	be = 7,
	/// Above (unsigned) (`CF=0 and ZF=0`)
	a = 8,
	/// Signed (`SF=1`)
	s = 9,
	/// Not signed (`SF=0`)
	ns = 10,
	/// Parity (`PF=1`)
	p = 11,
	/// Not parity (`PF=0`)
	np = 12,
	/// Less (signed) (`SF!=OF`)
	l = 13,
	/// Greater than or equal (signed) (`SF=OF`)
	ge = 14,
	/// Less than or equal (signed) (`ZF=1 or SF!=OF`)
	le = 15,
	/// Greater (signed) (`ZF=0 and SF=OF`)
	g = 16,
}
#[cfg(feature = "instr_info")]
#[cfg_attr(feature = "cargo-fmt", rustfmt::skip)]
static GEN_DEBUG_CONDITION_CODE: [&str; 17] = [
	"None",
	"o",
	"no",
	"b",
	"ae",
	"e",
	"ne",
	"be",
	"a",
	"s",
	"ns",
	"p",
	"np",
	"l",
	"ge",
	"le",
	"g",
];
#[cfg(feature = "instr_info")]
impl fmt::Debug for ConditionCode {
	#[inline]
	fn fmt<'a>(&self, f: &mut fmt::Formatter<'a>) -> fmt::Result {
		write!(f, "{}", GEN_DEBUG_CONDITION_CODE[*self as usize])?;
		Ok(())
	}
}
#[cfg(feature = "instr_info")]
impl Default for ConditionCode {
	#[cfg_attr(has_must_use, must_use)]
	#[inline]
	fn default() -> Self {
		ConditionCode::None
	}
}
// GENERATOR-END: ConditionCode

// GENERATOR-BEGIN: MandatoryPrefix
// ⚠️This was generated by GENERATOR!🦹‍♂️
/// Mandatory prefix
#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Hash)]
#[cfg(all(feature = "encoder", feature = "op_code_info"))]
pub enum MandatoryPrefix {
	/// No mandatory prefix (legacy and 3DNow! tables only)
	None = 0,
	/// Empty mandatory prefix (no `66`, `F3` or `F2` prefix)
	PNP = 1,
	/// `66` prefix
	P66 = 2,
	/// `F3` prefix
	PF3 = 3,
	/// `F2` prefix
	PF2 = 4,
}
#[cfg(all(feature = "encoder", feature = "op_code_info"))]
#[cfg_attr(feature = "cargo-fmt", rustfmt::skip)]
static GEN_DEBUG_MANDATORY_PREFIX: [&str; 5] = [
	"None",
	"PNP",
	"P66",
	"PF3",
	"PF2",
];
#[cfg(all(feature = "encoder", feature = "op_code_info"))]
impl fmt::Debug for MandatoryPrefix {
	#[inline]
	fn fmt<'a>(&self, f: &mut fmt::Formatter<'a>) -> fmt::Result {
		write!(f, "{}", GEN_DEBUG_MANDATORY_PREFIX[*self as usize])?;
		Ok(())
	}
}
#[cfg(all(feature = "encoder", feature = "op_code_info"))]
impl Default for MandatoryPrefix {
	#[cfg_attr(has_must_use, must_use)]
	#[inline]
	fn default() -> Self {
		MandatoryPrefix::None
	}
}
// GENERATOR-END: MandatoryPrefix

// GENERATOR-BEGIN: OpCodeTableKind
// ⚠️This was generated by GENERATOR!🦹‍♂️
/// Opcode table
#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Hash)]
#[cfg(all(feature = "encoder", feature = "op_code_info"))]
#[cfg_attr(all(not(feature = "exhaustive_enums"), has_non_exhaustive), non_exhaustive)]
pub enum OpCodeTableKind {
	/// Legacy encoding table
	Normal = 0,
	/// `0Fxx` table (legacy, VEX, EVEX)
	T0F = 1,
	/// `0F38xx` table (legacy, VEX, EVEX)
	T0F38 = 2,
	/// `0F3Axx` table (legacy, VEX, EVEX)
	T0F3A = 3,
	/// `XOP8` table (XOP)
	XOP8 = 4,
	/// `XOP9` table (XOP)
	XOP9 = 5,
	/// `XOPA` table (XOP)
	XOPA = 6,
}
#[cfg(all(feature = "encoder", feature = "op_code_info"))]
#[cfg_attr(feature = "cargo-fmt", rustfmt::skip)]
static GEN_DEBUG_OP_CODE_TABLE_KIND: [&str; 7] = [
	"Normal",
	"T0F",
	"T0F38",
	"T0F3A",
	"XOP8",
	"XOP9",
	"XOPA",
];
#[cfg(all(feature = "encoder", feature = "op_code_info"))]
impl fmt::Debug for OpCodeTableKind {
	#[inline]
	fn fmt<'a>(&self, f: &mut fmt::Formatter<'a>) -> fmt::Result {
		write!(f, "{}", GEN_DEBUG_OP_CODE_TABLE_KIND[*self as usize])?;
		Ok(())
	}
}
#[cfg(all(feature = "encoder", feature = "op_code_info"))]
impl Default for OpCodeTableKind {
	#[cfg_attr(has_must_use, must_use)]
	#[inline]
	fn default() -> Self {
		OpCodeTableKind::Normal
	}
}
// GENERATOR-END: OpCodeTableKind
